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? semiconductor msm548128bl 1/12 ? semiconductor msm548128bl 131,072-word 8-bit high-speed psram description the msm548128bl is a 1-mbit, high-speed and low power cmos pseudo static ram organized as 131,072-word 8-bit. the msm548128bl is fabricated using silicon gate n well cmos process. this process, coupled with single-transistor memory storage cells, permits maximum circuit density, minimum chip size, and high speed. msm548128bl has self-refresh mode in addition to address-refresh mode and auto-refresh mode. in self-refresh mode the internal refresh timer and address counter refresh the dynamic memory cells automatically. this series allows low power consumption when using standby mode with self-refresh. the msm548128bl also features a static ram-like write function that writes the data into the memory cell at the rising edge of we . the msm548128bl is pin compatible with cmos static ram and 256k pseudo static ram. features ? large capacity : 1-mbit (131,072-word 8 bits) ? fast access time : 70 ns max. ? low power : 200 m a max. (standby with self-refresh) ? refresh free : self refresh ? pin compatible : sram, 256k psram ? logic compatible : sram we pin, no address multiplex ? single power supply : 5 v 10% ? refresh : 512 cycle/8 ms auto-address refresh ? package compatible : sram standard package ? package options: 32-pin 600 mil plastic dip (dip32-p-600-2.54) (product : msm548128bl-xxrs) 32-pin 525 mil plastic sop (sop32-p-525-1.27-k) (product : msm548128bl-xxgs-k) xx indicates speed rank. product family family package access time (max.) msm548128bl-70rs MSM548128BL-80RS 600 mil 32-pin plastic dip 70 ns 80 ns msm548128bl-70gs-k msm548128bl-80gs-k 525 mil 32-pin plastic sop 70 ns 80 ns this version: jan. 1998 previous version: dec. 1996 e2l0043-17-y1
? semiconductor msm548128bl 2/12 pin name function a 0 - a 16 v ss v cc cs we oe ce rfsh i/o 0 - i/o 7 address input data input/output refresh input chip enable input output enable input write enable input chip select input power voltage (5 v) ground (0 v) pin configuration (top view) a 2 rfsh a 16 a 14 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 v ss v cc a 15 cs we a 13 a 8 a 9 a 11 oe a 10 ce i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32-pin plastic dip 32-pin plastic sop rfsh a 16 a 14 a 12 a 7 a 6 a 5 a 4 a 3 a 1 a 0 i/o 0 i/o 1 i/o 2 v ss v cc a 15 cs we a 13 a 8 a 9 a 11 oe a 10 ce i/o 7 i/o 6 i/o 5 i/o 4 i/o 3
? semiconductor msm548128bl 3/12 rfsh a 0 a 8 address latch control row decoder memory matrix (512 256) 8 i/o 0 i/o 7 input data control column i/o column decoder address latch control a 9 a 16 timing pulse generator read/write control refresh control ce cs oe we block diagram
? semiconductor msm548128bl 4/12 function table cs ( ce low) ce we mode l l i/o pin l h h rfsh l oe h h h x x l x x x l h x l x h x x x h l h x x x low-z high-z high-z high-z high-z high-z read write refresh standby cs standby l : low level input h : high level input x : dont care absolute maximum ratings electrical characteristics voltage on any pin from v ss *1 parameter symbol unit power dissipation rating operating temperature storage temperature storage temperature (biased) short circuit output current v t p d t opr t stg t bias i os C1.0 to 7.0 1.0 0 to 70 C55 to 125 C10 to 85 50 v w c c c ma recommended operating conditions parameter power supply voltage symbol unit v cc max. typ. min. input voltage v ss v ih v il 4.5 0 2.4 C0.5 5.0 0 5.5 0 6.0 0.8 v v v v (ta = 0c to 70c) *1 to v ss note: 1. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
? semiconductor msm548128bl 5/12 dc characteristics i sb1 parameter operating current symbol unit ma i cc1 ma min. standby current i cc2 m a i sb2 ma self refresh current i li m a i cc3 m a C10 input leakage current v ol output leakage current m a i lo C10 v output low level v oh v 2.4 output high level 60 1 typ. 100 1 100 85 2 max. 200 2 200 10 10 0.4 condition i i/o = open, t cyc = min. ce = v ih , rfsh = v ih , v in 3 0 v v cc = 5.5 v, v in = v ss to v cc oe = v ih , v i/o = v ss to v cc i ol = 2.1 ma i oh = C1 ma ce 3 v cc C 0.2 v, ce = v ih , rfsh = v il , v in 3 0 v ce 3 v cc C 0.2 v, v in 3 0 v, (v cc = 5 v 10%, v ss = 0 v, ta = 0c to 70c) rfsh 3 v cc C 0.2 v, v in 3 0 v rfsh 0.2 v capacitance c i/o parameter input capacitance symbol unit pf c in pf min. i/o pin capacitance typ. 8 10 max. condition v in = 0 v v i/o = 0 v note: this parameter is periodically sampled and is not 100% tested.
? semiconductor msm548128bl 6/12 ac characteristics measurement condition: input pulse level ........................... v ih = 2.4 v, v il = 0.4 v output reference level .................. v oh = 2.0 v, v ol = 0.8 v rising and falling time ................. 5 ns output load .................................... 1 ttl + 100 pf input timing reference level ........ high = 2.2 v, low = 0.8 v parameter symbol note t rc random read write cycle time unit ns msm548128bl-80 130 max. min. msm548128bl-70 120 max. min. t rwc random read modify write cycle time ns 190 170 t cea ce access time ns 80 70 t oea oe access time ns 30 30 t chz chip disable to output in high-z 6 ns 30 30 t clz ce to output in low-z ns 25 25 t ohz oe disable to output in high-z 6 ns 25 20 t olz oe output in low-z ns 0 0 t ce ce pulse width s 80n 10 m 70n 10 m t p ce precharge time ns 40 40 t as address set-up time ns 0 0 t ah address hold time ns 30 25 t rcs read command set-up time ns 0 0 t rch read command hold time ns 0 0 t wp write command pulse width ns 30 25 t cw chip enable time ns 80 70 t dw input data set-up time ns 25 25 t dh input data hold time ns 0 0 t ow output active from end of write ns 5 5 t whz write enable to output in high-z 6 ns 25 20 t t transition time 11 ns 350 350 t rfd rfsh delay time from ce ns 40 40 t fp rfsh precharge time ns 30 30 t fap rfsh pulse width (auto-refresh) s 30n 8 m 30n 8 m t fc auto-refresh cycle time ns 130 120 t rhc rfsh command hold time ns 15 15 t rcd rfsh delay time (standby mode) ns 5 5 t css cs set-up time ns 0 0 t csh cs hold time ns 30 25 t fas rfsh pulse width (self-refresh) m s 8 8 t rfs ce delay time from rfsh in self-refresh mode ns 160 150 t rfa ce delay time from rfsh in auto-refresh mode ns 0 0 t ref refresh period (512 cycle/8 ms) ms 8 8 (v cc = 5 v 10%, ta = 0c to 70c)
? semiconductor msm548128bl 7/12 notes: 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. 2. all voltages are referenced to ground. 3. i cc1 depends on output loading. specified values are obtained with the output open. 4. an initial pause of 100 m s is required after power-up followed by more than 8 initial cycles before proper device operation is achieved. 5. ac measurements assume t t = 5 ns. 6. t chz , t whz and t ohz define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. in write cycles, the input data is latched at the earlier rising point of either ce or we . write operation is achieved when both ce and we are low. 8. the i/o state remains at high impedance after ce goes low if the transition occurs at the same time as or after the falling edge of we . 9. use we or oe or both signals to disable the output before input data is applied during a write cycle when the input is not the same. 10. data input must be set to floating state before i/o becomes low impedance by we or oe or both. 11. v ih (min.) and v il (max.) are input timing reference levels for measurement. the transition time is measured between v il and v ih . 12. 512-cycle refresh must be applied within 15 m s after the end of self refreshing to satisfy 512 cycles/8 ms.
? semiconductor msm548128bl 8/12 timing waveform read cycle address a0 - a16 ce cs we oe rfsh d out t rc t ce t p t css t csh t as t ah t rcs t cea t rch t rhc t oea t rcd t olz t clz t chz t ohz valid data-out "h" or "l" write cycle 1 ( oe high) address a0 - a16 ce cs we oe rfsh d out t rc t ce t p t css t csh t as t ah t rhc t rcd "h" or "l" d in t cw t wp t dw t dh t whz t ohz t clz t ow t olz t chz valid data-in
? semiconductor msm548128bl 9/12 write cycle 2 ( oe low) address a0 - a16 ce cs we oe rfsh d out t rc t ce t p t css t csh t as t ah t rhc t rcd "h" or "l" d in t dw t dh t whz t clz valid data-in t wp t cw read modify write cycle address a0 - a16 ce cs we oe rfsh d out t css t csh t as t ah t rhc "h" or "l" d in valid data-in t rwc t p t rcs t wp t rch t ohz t rcd t oea t dw t dh t olz t clz t whz t ow t chz valid data-out
? semiconductor msm548128bl 10/12 auto refresh cycle self refresh cycle cs standby mode ce rfsh "h" or "l" t rhc t rfd t fc t fc t rcd t fap t fp t fap t rfa ce rfsh "h" or "l" t rfd t rcd t fas t rfs t rhc ce cs "h" or "l" t rc t ce t p t css t csh
? semiconductor msm548128bl 11/12 (unit : mm) package dimensions dip32-p-600-2.54 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 4.70 typ.
? semiconductor msm548128bl 12/12 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.32 typ. sop32-p-525-1.27-k mirror finish

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